Lattice MachXO3 FPGAs with very high density I/O from Mouser

The new Lattice Semiconductor MachXO3 Field Programmable Gate Arrays boast a very high gate density not usually found in programmable logic. These FPGAs feature low power consumption with almost instant-on activity after power-up. Densities in this FPGA family range from 640 to 6900 Look-Up Tables (LUTs). In addition to LUT-based low-cost programmable logic these devices also feature embedded block RAM (EBR) and distributed RAM. Internal phase locked loops (PLLs) reduce component count.

Advanced configuration support includes dual-boot capability and hardware versions of commonly used embedded blocks such as an SPI interface, two I2C interfaces, and a timer/counter. These features allow developers to quickly configure these devices for their applications without having to configure the FPGA for these commonly used logic blocks.

Enhanced flexibility in the I/O include drive strength control for driving external loads, slew rate control to compensate against high frequency oscillations, PCI bus compatibility, internal pull-up and pull-down resistors on the I/O pins, and open drain outputs for driving loads.

The MachXO3 is flexible enough to be used across many market segments including consumer, communications, data storage, industrial applications, and automotive applications.

Please follow the link to learn more about Lattice Semiconductor MachXO3 Field Programmable Gate Arrays, available from Mouser.