In the first CAN FD plug-fest, Bosch, Peak, and Vector proofed the interoperability of their CAN FD implementations. The FPGAs implementing the CAN FD data link layer as submitted for international standardisation were tested using different network topologies and transmission speeds. All nodes used a 40MHz clock frequency, an arbitration bit-rate of 500kbit/s sampled at 80 per cent and a data-phase bit-rate of 4Mbit/s sampled at 60 per cent.
The tests were performed with different busloads up to 100 per cent. The three nodes communicated in bus-line (9m) and passive star topologies (2 × 3m and 1 ×6 m). The passive star was terminated with 60Ohm at the center point. The next CAN FD plug-fest will take place in September. Parties interested in participation may contact CiA office. CiA plans a permanent CAN FD test environment for interoperability tests.
The CiA working group specifying CAN FD device and system design recommendations proposes a ration of 1:8 for arbitration/data-phase speed. In addition, the group will recommend bit-timings for different topologies as well as configuration registers for the CAN FD protocol controllers. CAN FD implementations should be clocked by 80, 40, or 20MHz in order to minimise timing problems.
For more information about the CAN FD plug-fest please go to www.can-cia.org.