How to reduce the time required for programming a PAC

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LabVIEW Real-Time 8.6 introduces powerful new features for programming the National Instruments CompactRIO programmable automation controller (PAC) that reduce development time and complexity, as well as providing tools for monitoring and maintaining CompactRIO applications.

How to reduce the time required for programming a PACNI CompactRIO is a high-performance programmable automation controller (PAC) that is highly differentiated by a field-programmable gate array (FPGA) at the heart of its architecture. At the highest level, an FPGA is a reprogrammable silicon chip. FPGAs provide the performance and reliability of custom hardware, while maintaining the flexibility of a software-defined system. Traditionally the use of FPGAs has been restricted to hardware design engineers who are experts in VHDL and other hardware descriptor languages; however, LabVIEW enables engineers to benefit from FPGAs without this expertise. LabVIEW is a powerful intuitive graphical programming language with hundreds of built-in control, analysis, communication, and logging functions. CompactRIO is entirely programmable with LabVIEW, including the FPGA, real-time processor, and human machine interface (HMI).

The new CompactRIO Scan Mode allows users to choose between accessing each I/O module directly in LabVIEW Real-Time and host applications with no FPGA programming or with LabVIEW FPGA for maximum flexibility and performance. New test panel and I/O forcing functionality enable users to get up and running quickly, perform advanced debugging, and monitor system performance.

Prior to the introduction of LabVIEW 8.6, CompactRIO I/O was first accessed by programming the FPGA, and then in LabVIEW Real-Time using the LabVIEW FPGA Interface VIs (virtual instruments). However, the new CompactRIO Scan Mode automatically detects the I/O modules and adds them to the LabVIEW project. Users can then drag-and-drop the I/O variables onto the LabVIEW Real-Time and host VI block diagrams and instantly read and write scaled, calibrated I/O data without any FPGA programming or compiling.

The I/O variable values are updated at a user-specified rate (up to 1kHz) by a new component called the NI Scan Engine, which runs in the background of LabVIEW Real-Time. All channel scans are hardware timed with module-to-module synchronisation. The scan engine can be configured from the LabVIEW project or programmatically with an included library of VIs. The scan engine also provides a Timed Loop timing source, enabling code to be synchronized with I/O updates for low-jitter control applications. Aliases of I/O variables can be created to provide an additional layer of abstraction from the physical I/O channel. Also, linear scaling can be enabled on I/O variables and aliases.

The new scan mode adds counter, quaduature encoder and PWM functionality to any existing eight-channel digital C Series module without requiring any programming. These speciality digital functions are configured from the LabVIEW project, but run on the FPGA for accuracy and speed. Now, without compiling, users can perform up to 1MHz edge counting, pulse width and frequency measurements, quadrature decoding and PWM control.

Counter-specific features are:

  • 1MHz counting on eight channels
  • 32-bit count register with programmable terminal count
  • Configurable terminal count and terminal count behaviour
  • Configurable count edge (rising, falling or both), source and gate
  • Period, PWM, and frequency measurements with configurable timebase

Quad-specific features are:

  • 1MHz maximum quad count rate
  • 32-bit count register
  • 32-bit velocity measurement register
  • Configurable velocity measurement timebase (256us, 512us, ... 16384us or 32768us)
  • X4 encoding
  • Two quad channels with A+B+Index inputs per module
  • Selectable encoder polarity
  • Ignores erroneous state transitions

PWM-specific features are:

  • Eight output channels
  • Per-channel duty-cycle and period configuration
  • Configurable frequency period (1Hz, 50Hz, 250Hz, 500Hz, 1kHz, 5kHz, 10kHz or 20kHz)

Easy to setup, debug and maintain

The NI Distributed System Manager, also new with LabVIEW Real-Time 8.6, provides a central location for monitoring systems on the network and managing published data. The new system manager provides test panels for CompactRIO modules using the new scan mode. As soon as a system is available on the network, users have access to real-time and historical-trend I/O values, enabling connections and signal integrity to be verified quickly. In addition to test panels, the System Manager also gives visibility into memory usage and processor load for CompactRIO controllers.

CompactRIO Scan Mode also introduces I/O forcing, which is a debugging tool that allows users to override the value of an I/O variable without stopping or changing the real-time application. Users can force inputs to test the response of their applications without a physical stimulus, as well as force outputs to override program output values. Channel values can be forced using the System Manager or with new I/O Forcing VIs.

Using LabVIEW FPGA with CompactRIO Scan Mode

With LabVIEW Real-Time 8.6, LabVIEW FPGA can be used in conjunction with the new scan mode on a per-module basis. Using LabVIEW FPGA, users can implement custom triggering, hardware-based analysis and signal processing, or high-speed analogue streaming. To use I/O modules in LabVIEW FPGA mode, users can simply drag the module to the FPGA target in the LabVIEW Project, removing them from scan mode. LabVIEW FPGA is then used to program the modules, while I/O variables are used to read and write I/O on the remaining modules.

When using LabVIEW FPGA Mode on one or more modules, the CompactRIO Scan Mode logic on the FPGA, known as the RIO Scan Interface (RSI), will be compiled with the LabVIEW FPGA VI into a single FPGA application. If no modules are configured to use scan mode, the RSI will not be included in the compile.

CompactRIO Scan Mode in detail

The new CompactRIO Scan Mode is powered by two technologies, the NI Scan Engine and the RIO Scan Interface. The RIO Scan Interface is a set of FPGA IP developed by National Instruments that is downloaded to the CompactRIO FPGA and is responsible for I/O module detection, timing, synchronisation and communication. The RIO Scan Interface runs a hardware-timed scan loop, which updates the physical I/O values. Two DMA channels are used to transport I/O data between the FPGA and real-time operating system (RTOS). The pre-built speciality digital functionality is also a component of the RIO Scan Interface.

The NI Scan Engine is a new component of LabVIEW Real-Time that runs at a priority above time-critical or between time-critical and timed structures, which is configurable by the user. Each time the RIO Scan Interface has finished the latest I/O scan LabVIEW adds the I/O variables to a global scan engine memory map and updates the values of all I/O variables concurrently. However, users can configure each I/O variable node to use either scanned access or direct access. By default, LabVIEW configures I/O variable nodes to use scanned I/O, which uses the scan engine memory map to perform non-blocking I/O reads and writes. Direct I/O access bypasses the scan engine memory map and communicates directly with the I/O device driver to perform blocking I/O reads and writes. The NI Scan Engine also publishes the I/O variables to the network, making them available for reading and writing in host applications, test panels, and I/O forcing. Network publishing of an I/O variable is handled by the scan engine process, not the Shared Variable Engine, and can be disabled from the I/O variable properties page.

When LabVIEW FPGA is used in conjunction with scan mode (some modules using scan mode and some using LabVIEW FPGA Mode) the RIO Scan Interface and the FPGA VI are compiled into a single bit stream and deployed to the FPGA. Modules in LabVIEW FPGA Mode are accessed in LabVIEW Real-Time using the FPGA Interface VIs, while I/O variables are used for the I/O modules using scan mode. If all modules are removed from scan mode, then the RIO Scan Interface is not compiled into the bit stream. The space consumed by the RIO Scan Interface, on the FPGA, scales with the number of modules using scan mode.

When to use CompactRIO Scan Mode

CompactRIO Scan Mode is designed for applications requiring synchronous I/O updates at rates of up to 1kHz. The speciality digital functionality provided by scan mode can be used to convert any existing eight-channel digital I/O module into an advanced PWM, counter or quaduature encoder module. Using the I/O forcing and test panel functionality of the system manager, scan mode can also be used for initial setup, monitoring system performance, and performing advanced troubleshooting. For applications with higher performance requirements, such as analogue streaming at nearly 1MHz, high-speed PID control loops over 1kHz, custom hardware analysis and signal processing, or I/O modules not supported by scan mode, use the LabVIEW FPGA Module in conjunction with scan mode. The LabVIEW FPGA Module can also be used to offload processing from the real-time controller.

Scan mode is supported by controllers running the VxWorks RTOS with at least 2M gate FPGAs due to the FPGA space requirements of the RSI. Supported controllers include the NI 9014, NI 9012, NI 9074, and NI 9073. Supported backplanes include the NI 9103, NI 9104, NI 9074, and NI 9073.

There are some performance trade-offs when using CompactRIO Scan Mode. For example, the speciality digital functionality supports up to 1MHz counters, versus 20MHz counters achievable with LabVIEW FPGA. The scan engine uses system resources, which include FPGA space, two DMA channels, memory and an amount of CPU time that scales with the scan rate. The space consumed by the RSI, on the FPGA, scales with the number of modules using scan mode.


LabVIEW Real-Time 8.6 adds a powerful set of features designed to reduce CompactRIO development time and complexity. The new scan mode allows users to access I/O in LabVIEW Real-Time and host applications with no FPGA programming, while also providing the option to program the FPGA directly for the most advanced requirements. The NI Distributed System Manager and I/O forcing also bring test panels and advanced debugging to CompactRIO, making it easy to monitor and maintain CompactRIO applications.

For more information about LabVIEW 8.6, go to or use the form on this page.

04 August 2008

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